1. Field of the Invention
This invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, this invention relates to a Field Programmable Gate Array having a non-volatile user memory. Still more particularly, this invention relates to configuring an FPGA and storing data in the non-volatile user memory in the FPGA.
2. Background
Programmable logic devices are known in the art. Programmable logic devices include complex programmable logic device (CPLD), Field-programmable gate array (FPGA), and other configurable integrated circuits known in the art. An FPGA is the most complex type of programmable logic device, comprising any number of logic modules, an interconnect-routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. To implement a particular circuit function, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit.
An FPGA includes an array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. Programmable routing lines link the cells to one another. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing Boolean functions of multiple variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain a plurality of flip-flops. Two types of logic cells found in FPGA devices are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
An FPGA circuit can be programmed to implement virtually any set of digital functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers referred to as input/output ports (I/Os). Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation, and hysteresis. The input/output ports provide the access points for communication between chips. I/O ports vary in complexity depending on the FPGA.
FPGAs may be customized by a user to perform a wide variety of combinatorial and sequential logic functions. Numerous architectures for such integrated circuits are known. Examples of such architectures are found disclosed in U.S. Pat. No. 4,870,302 to Freeman, U.S. Pat. No. 4,758,745 to El Gamal et al., and U.S. Pat. No. 5,132,571 to McCollum et al., as well as many others. The architecture employed in a particular FPGA integrated circuit will determine the richness and density of the possible interconnections that can be made among the various circuit elements disposed on the integrated circuit and thus profoundly affect its usefulness.
Non-volatile memories, such as flash memories are known in the art. Flash memories are electrically erasable and are generally used to store data where it is undesirable that the data be lost when the device is not connected to a power source. Non-volatile memories are often used to store the configuration data for FPGAs such as SRAM FPGAs that are based on volatile technology. Configuration data may be loaded from a flash memory into an SRAM-based FPGA each time the FPGA is powered up. Other flash memory devices are used in systems to store user data. User data is data generated or used in the operation of an FPGA device, as opposed to configuration data which is used to configure the programmable logic and routing to define the function of the FPGA.
Programmable logic devices available from Lattice Semiconductor Corporation, Hillsboro, Oreg. and Altera Corporation, San Jose, Calif. use on-chip blocks of flash memory to load and control SRAM programmable elements in single chips. For example, the ispXP (eXpanded Programmability) product available from Lattice Semiconductor combines electrically-erasable-programmable-read-only memory (EEPROM) and SRAM technologies. These types of programmable logic devices add an advantage of not needing a separate non-volatile memory chip, but the SRAM programmable logic configuration still has to be loaded from the non-volatile memory block during power-up.
An example of a semiconductor device 700 employing on-board non-volatile memory to load configuration data into an SRAM programmable logic unit 702 is shown in FIG. 1. Non-volatile EEPROM array 50 stores the device configuration. At power-up, this information is transferred in a parallel fashion into SRAM cells 704 in the programmable logic unit 702. The loading of the configuration data from the non-volatile memory 50 into the SRAM programmable logic 702 may be performed under the control of control logic 720. JTAG port 730 and system configuration port 740 allow for in-system programming.
Field Programmable Gate Arrays (FPGAs) including volatile memories that are available to store user data are known in the art. SRAM-based FPGAs such as those, for example, available from Xilinx Corporation, San Jose, Calif. include SRAM-based volatile memory blocks. Some of these blocks may be available for user data. Even on non-volatile FPGAs, however, such as antifuse-based FPGAs, the memory blocks are volatile (generally SRAM-based). Prior art FPGAs do not, therefore include on-chip non-volatile memories available for storing user data.
It is a problem in FPGAs containing volatile logic and memory that the FPGA must be programmed each time the device is powered up. Thus, the configuration data and any user data must be stored in a memory outside the FPGA. Thus, power up of the FPGA is slow and requires an excessive amount of power in order to receive configuration and user data over the Input/Output (I/O) of the FPGA.
Furthermore, since all the configuration memory and user data must be loaded using the I/O of the FPGA, security of the data is a problem. Security is a problem because the wires connecting the I/O of the FPGA to the system loading the data may be easily tapped. Thus, those skilled in the art are continually looking for ways to provide an FPGA that provides a fast, secure, power up with relatively low power consumption.